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\textbf{\large THE UNIVERSITY OF ADELAIDE}\\

\textbf{SCHOOL OF ELECTRICAL \& ELECTRONIC ENGINEERING}

{\small ADELAIDE, SOUTH AUSTRALIA, 5005}

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\textsc{Implementation Plan}
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\textbf{\LARGE MIPS Microprocessor\\(Cache Circuits)}

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\textbf{Joel Stanley, Rhys Bowden, Melanie Say Wei Tan, Robert Moric}

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\textbf{\large ELEC ENG 4039 A/B HONOURS PROJECT}

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\textbf{B.E. in Electrical and Electronic Engineering\\
B.E. in Computer Systems Engineering\\
B.E. in Telecommunications Engineering\\}
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Each student at Level IV of the course in Electrical and
Electronic Engineering, Computer Systems Engineering and
Telecommunications Engineering is required to complete this course.
The course involves approximately 240 hours of project work over the
whole academic year.  Students are assessed on their performance in
the project, a written proposal, this written report, a technical
paper, and two seminar presentations.

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Date submitted:

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Supervisor:

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Signature of Supervisor:
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\section*{Objectives}
The MIPS architecture is popular Reduced Instruction Set Computer (RISC) microarchitecture, utilised in many commodity hardware systems.
\\In collaboration with Dr David Money Harris' VLSI Design class from Harvey Mudd College, California, the project involves implementation of the MIPS R2000-class microprocessor to be fabricated by MOSIS. Our team will focus on the cache memory system, followed by projects utilising the fabricated hardware.
\\The testbed containing the microprocessor and supporting peripherals will be packaged in a form that will enable it to be used as a promotional tool, as well as for demonstrating the unit.

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\section{Background and Significance}

The first aim of this project is to co-operate with the VLSI class
from Harvey Mudd College, California, to design and build a MIPS-based
microprocessor.

Microprocessors are electronic devices that contain all the functions
of a CPU on a single integrated circuit. This microprocessor will be
split into a control unit, a coprocessor and a data path. The datapath
contains a fetch, decode, execute and memory stage. The Adelaide team
is designing the 512kB cache for the memory stage. A cache stores
recently used memory data on chip to save slow memory accesses. The
cache is direct mapped, meaning that each datum from memory has a
unique place it can be stored in the cache.

The chip will use a MIPS R2000 instruction set architecture
(ISA). MIPS stands for Microprocessor without Interlocked Pipeline
Stages. The MIPS ISA is a popular RISC microprocessor
architecture. R2000 has 32-bit instructions including various loads,
stores, arithmetic, jumps and branches, shifts, moves and exceptions.

In the production of a microprocessor testing is required on both the
design and the finished hardware.

\section{Project Specifications}

\subsection{Final Deliverables}
\begin{enumerate}[{[D}1{]}]
\item Hardware Presentation of the MIPS-based microprocessor
\item Package of testing tools and report on test results
\item Extension: Report examining low power design alternatives
\end{enumerate}

\subsection{Requirements}
\begin{enumerate}[{[R}1{]}]
\item Hardware demonstration
  \begin{itemize}
  \item Running an interactive program (possibly a Web-server or
    ELIZA).
  \item Robust packaging so that the demonstration is easy to
    move and set up.  
  \item Uses MIPS-based microprocessor.
  \end{itemize}

\item Testing tools
  \begin{itemize}
    \item Software tests of design using either fast SPICE or IRSIM,
      depending on availability.
    \item Documentation for software testing.
    \item Detailed methods of hardware testing.
  \end{itemize}
\item Extension: Report on low power
  \begin{itemize}
  \item Examination of MIPS based microprocessor.
  \item Development of alternative designs to achieve low power.
  \item Examination and evaluation of alternative designs
  \end{itemize}
\end{enumerate}

\subsection{Reporting Requirements}

First Semester
\begin{description}
\item[Week 4 Project Implementation Plan:] A plan detailing what is to
  be accomplished during the project, and how the group intends to do
  it.
\item[Week 5 Proposal Seminar:] Presents and explains the intended
  project including requirements and what will be produced.
\item[Week 8 Critical Design Review:] Evaluate and assess intended
  design(s) for project.
\item[Week 10 Submit Peer Review:] Review another group's project.
\item[Week 12 Project Log Book:] A record of all meetings and time
  spent on the project.
\end{description}

Second Semester
\begin{description}
\item[Week 9 Final Project Report and Technical Paper due:] The final
report covering the completed project and the process of producing it.
\item[Week 10 Final Project Seminars:] A seminar on the completed
project.  
\item[Week 11 Project Exhibition:] Displaying the project to the
public.
\end{description}

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\bibitem{Green07} C.~A.~Green, \emph{Final Year Honours and Design
  Project Handbook}, 2007, http://www.eleceng.adelaide.edu.au/students/undergrad/courses/4039/material/notes/

\bibitem{various07} Various, \emph{HMC-MIPS Wiki Design Sketches},
2007, http://code.google.com/p/hmc-mips/wiki/DesignSketches

\bibitem{hmcmemsys} Various, \emph{HMC-MIPS Wiki Memory System Specifications},
2007, http://code.google.com/p/hmc-mips/wiki/MemorySystemSpecifications

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